zlacker

What about RISC-V?

>>netr0u+(OP)
We also have a CHERI-RISC-V specification (https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf), with support in CHERI LLVM, CHERI QEMU and CheriBSD, plus three open-source FPGA implementations (https://github.com/CTSRD-CHERI/Piccolo, https://github.com/CTSRD-CHERI/Flute, https://github.com/CTSRD-CHERI/Toooba) that span various parts of the microarchitecture design space, and it is the platform we use for our own research on architecture and microarchitecture. But for various reasons (e.g. proximity to the university, existence of competitive microarchitectures several years ago, ISA and ecosystem maturity, enthusiasm and interest on their part) Arm was the right partner for this program.

>>jrtc27+V5
Then the HN title is inaccurate.

>>netr0u+D7
Are you saying Arm haven't released a CHERI enabled Morello board?

>>netr0u+D7
The HN title is literally the title of the post (if you had taken the 2s to actually open the link), since Arm was the one to release the board, and just because RISC-V specifications, models, implementations, etc., exist, doesn't mean that Arm wasn't involved...

>>klelat+n9
It's technically true, but it makes it look like CHERI is only for ARM.

>>netr0u+sa
I don't see why it implies that. "Arm releases experimental DDR5-enabled $NAME board" wouldn't make it sound like DDR5 is only for Arm, so why would "Arm releases experimental CHERI-enabled Morello board"?

>>netr0u+sa
The HN title is an accurate reflection of the article and the event. When the RISC-V group has a similar event, there will be a similar article. Nothing deceptive or incorrect here.