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[parent] [thread] 5 comments
1. netr0u+(OP)[view] [source] 2022-01-20 14:55:43
Then the HN title is inaccurate.
replies(2): >>klelat+K1 >>xenocr+32
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2. klelat+K1[view] [source] 2022-01-20 15:04:15
>>netr0u+(OP)
Are you saying Arm haven't released a CHERI enabled Morello board?
replies(1): >>netr0u+P2
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3. xenocr+32[view] [source] 2022-01-20 15:06:00
>>netr0u+(OP)
The HN title is literally the title of the post (if you had taken the 2s to actually open the link), since Arm was the one to release the board, and just because RISC-V specifications, models, implementations, etc., exist, doesn't mean that Arm wasn't involved...
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4. netr0u+P2[view] [source] [discussion] 2022-01-20 15:09:06
>>klelat+K1
It's technically true, but it makes it look like CHERI is only for ARM.
replies(2): >>jrtc27+Lb >>dev_tt+1X
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5. jrtc27+Lb[view] [source] [discussion] 2022-01-20 15:49:10
>>netr0u+P2
I don't see why it implies that. "Arm releases experimental DDR5-enabled $NAME board" wouldn't make it sound like DDR5 is only for Arm, so why would "Arm releases experimental CHERI-enabled Morello board"?
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6. dev_tt+1X[view] [source] [discussion] 2022-01-20 19:14:28
>>netr0u+P2
The HN title is an accurate reflection of the article and the event. When the RISC-V group has a similar event, there will be a similar article. Nothing deceptive or incorrect here.
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