Remote: Yes
Willing to relocate: Yes
Technologies: UVM, Verilog, System Verilog, C++/C, Python
Résumé/CV: https://drive.google.com/file/d/10jeoW7V63fJu4dww78kYVLibcAt...
Email: https://veilmail.io/e/_wxQAD
I am currently in my final semester and looking for entry level job in RTL design or in design verification. I have good understanding in ASIC design, synthesis and UVM. I am a F1 student and would require sponsorhip in future, please feel free to contact me to discuss further about my qualification. Looking forward to connect with you all.