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1. transp+(OP)[view] [source] 2022-01-20 16:12:31
Hopefully ARM's MTE (memory tagging extension) will appear in Apple's 2022 SoCs (M2, A16), https://security.googleblog.com/2019/08/adopting-arm-memory-...

(2020) CheriBSD port to Morello, https://www.youtube.com/watch?v=7aVygpgkm1

(2021) GCC support for Morello, https://gcc.gnu.org/pipermail/gcc/2021-July/236868.html

(2021) OSS desktop software stack, https://www.capabilitieslimited.co.uk/pdfs/20210917-capltd-c...

> We measure a 0.026% Lines-of-Code (LoC) change rate in approximately 6 million lines of C and C++ code to introduce CHERI memory safety. In our review of past vulnerabilities, we see likely mitigation rates of 91% for X11, 82% for Qt, 43% for KDE, and 100% for other supporting libraries (typically image processing).

(2022) Microsoft Research, https://msrc-blog.microsoft.com/2022/01/20/an_armful_of_cher...

> We can implement this model on a variety of mechanisms, such as MMU-based isolation or software fault isolation, but expect that CHERI will provide better performance and scalability than anything on current commodity hardware ... If the Morello program can demonstrate that CHERI meets the performance goals for real-world use then it is a game changer for security, deterministically preventing spatial safety vulnerabilities and (with software support) heap temporal safety bugs, dramatically reducing the set of bugs that become exploitable as for anything other than denial of service.

replies(1): >>pjmlp+j2
2. pjmlp+j2[view] [source] 2022-01-20 16:21:39
>>transp+(OP)
They already have PAC, although not exactly the same.
replies(1): >>saagar+PZ
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3. saagar+PZ[view] [source] [discussion] 2022-01-20 20:42:01
>>pjmlp+j2
Right. PAC is largely used for CFI, CHERI/MTE are more general memory corruption mitigations.
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