One of the great things about writing the core in C and then either optimizing for the compiler or writing the inner loop in the target ISA is that one can adapt with the CPU architecture. Anyone who has done development for true high performance architectures knows that you need to optimize for memory architecture as much as CPU architecture. When the new Xeons come out with double the L2 and a larger cache line and X cores in NUMA layout, writing everything in the Pentium 3 ISA is going to look pretty stupid.