RISC-V is a free and open instruction set architecture (ISA). People can go ahead and build open-source implementations, closed-source implementations, licensed implementations. This is very different than ARM, where you can only buy implementations from ARM, or if you happen to be one of a handful of selected companies with an ARM architectural license (which costs $$$$$), you can build your own implementation, but they still have to meet certain specifications as dictated by ARM. People can freely implement RISC-V processors, extend them, and play around with it. We think RISC-V has a big potential to unleash innovation. As a matter of fact, we believe this is the prerequisite.
SiFive has made the RTL open-sourced that went into FE310. We think this is a big deal, because other SoCs don't open-source their RTL.