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1. e12e+(OP)[view] [source] 2015-10-29 02:11:12
Right. Which is of course why we have stuff like the NASA/ESA making and releasing designs - big government projects with highly skilled staff. But they don't have much interest in releasing a "personal computer" or a "smart phone" (I'm sure they'd love to have an open hw platform to use for smart phones and tablets - or work stations and super computers, just that it's not high up on the list of priorities in the "millions of dollars" budget lists).

[ed: I'm thinking of things like LEON etc - but as mentioned, and as I understand it, for the ASIC case, maybe not the whole eval board is open. And it's not really in the same ballpark as the dual/quad multi-GHz cpus we've come to expect from low-end hard-ware:

http://www.gaisler.com/index.php/products/boards/gr-cpci-leo... ]

replies(1): >>nickps+P2
2. nickps+P2[view] [source] 2015-10-29 03:01:04
>>e12e+(OP)
Oh, let me be clear that any starting point will definitely have more work to do and will never be in ballpark as top Intel/AMD/IBM CPU's. The reason is that they use large teams of pro's with the best tools often doing full-custom HW development. Full-custom means they'll do plenty to improve HDL, RTL, and even wiring of gates they use. Think of Standard Cell as Java web applications with full custom being like delivering a whole platform with a board, firmware, assembler, OS components, and native applications. That's maybe illustrative of the differences in skills and complexity.

Example of custom design flow http://viplab.cs.nctu.edu.tw/course/VLSI_SOC2009_Fall/VLSI_L...

Note: Load up this right next to the simple, 90nm MCU PDF I gave you and compare the two. I think that you'll easily see the difference in complexity. One you'll be able to mostly follow just googling terms and understand a lot of what they're doing. You're not going to understand the specifics of the full-custom flow at all. Simply too much domain knowledge built into it that combines years of analog and digital design knowledge. Top CPU's hit their benchmarks using full-custom for pipelines, caches, etc.

Example of verification that goes into making those monstrosities work:

http://fvclasspsu2009q1.pbworks.com/f/Yang-GSTEIntroPSU2009....

So, yeah, getting to that level of performance would be really hard work. The good news is that modern processors, esp x86, are lots of baggage that drains performance that we don't need. Simpler cores in large numbers with accelerators can be much easier to design and perform much better. Like so:

http://www.cavium.com/OCTEON-III_CN7XXX.html

Now, that's 28nm for sure. Point remains, though, as Cavium didn't have nearly the financial resources of Intel despite their processors smoking them in a shorter amount of time. Adapteva's 64-core Epiphany accelerator was likewise created with a few million dollars by pro's and careful choice of tooling. So, better architecture can make up for the lack of speed that comes from full-custom.

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