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1. cpgxii+(OP)[view] [source] 2025-12-03 18:09:40
RISC-V the ISA is open; RISC-V implementations need not be. There's no reason to believe that any truly high-performance implementations will be usefully open.
replies(2): >>echelo+w >>xpuent+c3
2. echelo+w[view] [source] 2025-12-03 18:12:01
>>cpgxii+(OP)
And since China has such a lead, you'll be using their implementations.

That's why this is geopolitical.

The DoD and Five Eyes prefer ARM, where the US maintains a strong lead.

3. xpuent+c3[view] [source] 2025-12-03 18:25:37
>>cpgxii+(OP)
There are also many high-performance Chinese implementations that are open-source (e.g., XuanTie C910, XiangShan, etc.).

While achieving an open-core design comparable to Zen 5 is unlikely in the near term, a sustained open-source collaborative effort could, in the long run, significantly change the situation. For example, current versions of XiangShan are targeting ~20 SPECint 2006/GHz (early where at ~9).

replies(1): >>echelo+64
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4. echelo+64[view] [source] [discussion] 2025-12-03 18:30:11
>>xpuent+c3
Yeah, but then the US doesn't get to spy on you anymore ;)

Stuff tends to stay open until a new leader emerges. Then the closed source shell appears.

We've seen this with the hyperscalers and in a million other places.

Use open to pressure and weed out incumbents and market leaders. Then you're free to do whatever.

So we'd be replacing NSA spying with MSS spying.

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