zlacker

>>evakho+(OP)
> I like the Raspberry Pi RP2040 a lot. It's relatively cheap (around $1 USD) and has tons of on-board RAM - 264 KB in fact! It also has what is called Programmable IO, or PIO.

I wonder how benchmarks would compare between the RP2040 and, say, a Z80.

>>zahlma+4h
The RP2040 is a Cortex-M0, which is about the smallest core you find on modern systems but still a pipelined 32 bit RISC machine running in the dozens of MHz.

Note though, that the article is really about the PIO device on these SOCs', which isn't part of the main CPU at all. It's sort of a very limited programmable hardware engine for the specific task of doing PCB level interconnect using GPIO and lightly buffered streaming. In some sense it's like a thematic midpoint between an FPGA and a CPU.

It's... honestly it's just really weird. And IMHO has really, really, REALLY limited application. It's for people who would otherwise be tempted to bitbang an I2C or UART, but not for ones who can put hardware on the board themselves, or who have a FPGA handy, or even for people who want to do non-trivial stuff like QSPI displays[1] or whatnot.

Basically PIO smells like a wart to me. I genuinely don't know who wants it. Regular hackers aren't sophisticated enough to use it productively and the snobby nerds have better options.

[1] The linked article appears to be doing a quarter-VGA display in 3-bit/8-color, and is sort of right at the limit of the power of the engine.

>>ajross+Aw

  >Basically PIO smells like a wart to me. I genuinely don't know who wants it. Regular hackers aren't sophisticated enough to use it productively and the snobby nerds have better options.

what are you blathering on about, sir?

driving complex displays with no spu use: https://dmitry.gr/?r=06.%20Thoughts&proj=09.ComplexPioMachin... (my work)

pretending to be memory stick and sd card at dozens of mhz as a slave to a sync bus (my work)

ethernet: https://github.com/kingyoPiyo/Pico-10BASE-T (not my work)

68k bus slave (my work)

usb host https://github.com/sekigon-gonnoc/Pico-PIO-USB (not my work)

all on a $1 chip

>>dmitry+3D
> what are you blathering on about, sir?

Please don't.

I mean, I applaud your work. But let's also be honest (in the "tough love" sense): those are all toys with significant limitations that preclude anyone shipping any of them on an actual device to an actual consumer. I mean, your SOC (maybe a $2 one) surely already includes a SPI master and USB host!

Actual interconnects that solve real market problems have big boring spec books and competing implementations and silicon vendors. The application for PIO is basically limited to "I have to connect to this crazy old junk and no one makes the part I'd otherwise need".

>>ajross+zG
if you find a SoC for $1 that has 2 Ethernet ports, and a usb host on it, while also having two cores and supporting 32MB of RAM you'll surprise me. rp2350 does all of the above for $1

>>dmitry+L51
Have you tested out the 2x PSRAM configuration; if so, have you written anything up about it? :) I've thought about a configuration like that myself but haven't committed to any hardware yet.

>>duskwu+Cb1
yes i have tested it and no i have not written about it (yet). it does work and with the new ISSI 16MB chips, it gives 32MB of continuous memory!

>>dmitry+su1
Awesome - I might just have to try it.

How are you handling startup? The approach I had in mind was putting boot flash on the second channel with a separate CS pin from PSRAM and configuring that in OTP; any idea if that would work?

>>duskwu+mv1
Yes, sort of. Basically a tiny loader in OTP that enables nCS1 on some pin, copies code from there to ram on nCS0, reconfigures nCS1 to point to second ram. This does break usb flashing. Use swd.

>>dmitry+sA1
Is there no way to do that without code in OTP? The bootrom is supposed to scan for an IMAGE_DEF on both memory banks, and can use nCS1 as specified in FLASH_DEVINFO. Unless there's something I'm missing, that should be sufficient.