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[return to "Arm releases experimental CHERI-enabled Morello board"]
1. fulafe+Kn[view] [source] 2022-01-20 13:59:03
>>zxombi+(OP)
How does it compare to previous proposed hw assisted ways to bolt memory safety onto C? Like Hardbound, In-Fat, MPX for example.
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2. mwcamp+so[view] [source] 2022-01-20 14:01:53
>>fulafe+Kn
I'll leave it to others to go into technical details, but the most obvious answer is that this effort has major industry players behind it, meaning it might actually make it into production.
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3. pjmlp+0M[view] [source] 2022-01-20 15:54:11
>>mwcamp+so
As mentioned in another reply, there are already a couple of tagging approaches in production.

Unfortunely x86/x64 don't have any, and MPX was broken from the get go.

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4. aseipp+Jk1[view] [source] 2022-01-20 18:23:01
>>pjmlp+0M
This isn't a memory tagging system at all and has capabilities far beyond that (pun intended), so I don't know why whatever other approaches like MTE are out in the wild are relevant.
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5. jrtc27+3m1[view] [source] 2022-01-20 18:30:27
>>aseipp+Jk1
They're relevant because they're technologies relating to memory safety and provide some level of additional protection. However, they rely on secrets and are in general only probabilistic, so they don't deterministically mitigate all memory safety issues (you can deterministically mitigate some with clever allocations of memory "colours", but not all). CHERI and MTE-like schemes also both rely on the use of tagged memory, but in rather different ways.
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